Integrated circuits (chips) relentlessly continue increasing in device count and complexity. While this ongoing progress births a myriad of new hardware and software capabilities, such expansion is not without cost. Burgeoning integrated circuit die sizes consume precious silicon real estate. Also, higher device counts and device densities made possible by technological advances result in greater power consumption per die, thus reducing battery lives and increasing heat dissipation problems.
Against such concerns for silicon real estate and chip power consumption, the enormous task of testing these complex integrated circuits must be weighed. Indeed, the problem of testing also grows with device complexity. Exhaustive testing of chips becomes intractable, if not outright impossible, where millions of internal nodes must be tested through only hundreds of interface nodes (pins). Additionally, new packaging techniques such as flip-chip mounting complicate probing and other specialized techniques for observing internal integrated circuit nodes in packaged and/or operational devices.
Consequently, it has long been recognized that increased visibility into the internal states of integrated circuits can provide a great boon to testing efforts. Various techniques of scanning logic values into and out of the core of an integrated circuit have been in use since at least the early 1970's (see, e.g., U.S. Pat. No. 3,761,695 entitled "Method of Level Sensitive Testing a Functional Logic System" by Eichelberger).
Prior art scan latches such as the one shown in FIG. 1 typically employ static design principles and consequently do not necessarily minimize the number of devices needed to provide the test capabilities of the illustrated design. The prior art scan circuit includes a master stage 100 and a slave stage 110, each having a connection to a storage node 105 driven by a data latch 115 during normal operation. Since the slave stage 110 drives a slave stage output node 120 at all times, regardless of the data origin or the clock states, the scan latch is considered a static scan latch.
Data from the data latch 115 represents data which passes through combinational logic circuits during normal operation of the chip. When a core clock signal (CLK) is high, the clock signal and an inverted clock signal generated by an inverter 130 cause data from a data input (DIN) to pass through a pass gate 125. During normal operation, scan clock A (SCA) is low, SCA# generated by an inverter 150 is high, and cross-coupled tri-state inverters 134 and 132 sustain the data when CLK falls. An inverter 136 drives the value to a subsequent combinational logic block CB 138 and to a latch 140.
In a test mode, data can be scanned in from a serial input (SI) when scan clock A is high. The tri-state inverter 134 is disabled and the storage node 105 is driven by an inverter 152 from the serial input through a pass gate 156. In another test mode, data can be scanned out from the storage node 105 when scan clock B (SCB) is driven high. A pass gate 162 is enabled when scan clock B is high and SCB#, generated by an inverter 160, is low. An inverter 166 and a tri-state inverter 164 sustain the data when SCB falls. Data is driven to the slave stage output node 120 by an inverter 168 and can be shifted out through a subsequent master stage 170 and other subsequent stages by alternating SCA and SCB.
Again, this prior art scan latch is a static scan latch because the inverter 168 continuously drives the slave stage output node 120. Such a static design results in the addition of twenty transistors per data latch, eighteen of which are included in the master and slave stages, with the two additional devices included in this case to make the inverter 134 in the data latch a tri-state inverter.
The prior art has clearly recognized the importance of scan based design. In light of the high device overhead of adding scan to a design, any reduction in scan cell size could greatly reduce costs where scan is employed extensively. Additionally, reducing power consumption in elements as pervasive as scan cells helps reduce the overhead associated with a scan based design. The prior art, however, has not adequately addressed these concerns. In particular, the prior art has failed to utilize dynamic scan latches to reduce device count in the scan latch slave.